I have tried running this latest set of tests both with and without the crystal. I removed the crystal and capacitor from the BM6000 board and used this for the external test. I have some reservations about running this in a breadboard setup, but it is what it is.
My logic may be flawed, but running without the crystal should give an indication of how the I/O initializes from purely a electrical circuit standpoint. With the crystal, I would expect to get an indication of what the software is doing. I don't really know what happens in the grey area in-between the two, or if there is a grey area. My recollection is that microprocessors of this era just started running whatever op codes were stored at address 0x0000 when powered on.
In the traces posted earlier, the reset signal is simply tied to the power signal. I know that this is not the ideal situation. I would have rather been able to generate a delayed signal that was triggered from the power signal, but I don't think that it is possible with the test equipment that I'm using. If the RESET signal looks early, it is likely an anomaly related to how the test equipment scans or displays the signal.
I did a quick test by manually changing the reset signal (plugging in a jumper on the breadboard).
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Except for the FreqCount signal, all of the signals usually remained unchanged. The FreqCount typically goes high for a random period of time, then returns to zero. I'm not sure what to surmise from this behavior.
I expected to see the outputs update as a group (of 8), but not all of the bits being the same value. For example, in the Data Strobe set of signals, I expected to see something other than 0 or 7 (all zeros or ones), which would indicate that the software was polling the keyboard or setting a particular LED display.
I don't have any real experience with trying to debug a faulty CPU. Typically, at work, if a circuit/CPU was acting flaky, we trashed it and replaced it with a new one, or sent it back to the hardware group that likely did the same.
I didn't expect my bench test to produce the behavior of a properly functioning CPU in a BM6000. It would be a very difficult to replicate the exact timing of all of the signals such that the diagnostics were happy. I did expect that the results from a given test would be fairly repeatable.
It seems like the CPU is running random assembly code. So far, it has not hit a HCF opcode, but it feels like it is just a matter of time ;-).
Glitch